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sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 1 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 synchronous buck regulator 24 v input, 24 a (sic431) description the sic431 is a synchronous buck regulator with integrated high side and low side power mosfets. its power stage is capable of supplying 24 a continuous current at up to 1 mhz switching frequency. this regulator produces an adjustable output voltage down to 0.6 v from 3 v to 24 v input rail to accommoda te a variety of applications, including computing, consumer electronics, telecom, and industrial. sic431s architecture supports ultrafast transient response with minimum output capacitanc e and tight ripp le regulation at very light load. the device is internally compensated and no external esr network is required for loop stability purposes. the device also incorporates a power saving scheme that significantly increases light load efficiency. the regulator integrates a full protection feature set, including output over voltage protection (ovp), cycle by cycle over current protection (ocp) short circuit protection (scp) and thermal shutdown (otp ). it also has uvlo and a user programmable soft start. the sic431 is available in le ad (pb)-free power enhanced mlp44-24l package in 4 mm x 4 mm dimension. applications ? 5 v, 12 v, and 24 v input rail pols ? desktop, notebooks, server, and industrial computing ? industrial and automation ? consumer electronics features ? versatile - operation from 3 v to 24 v input voltage - adjustable output voltage down to 0.6 v - scalable solution 8 a (sic438), 12 a (sic437), and 24 a (sic431) - output voltage tracking and sequencing with pre-bias start up - 1 % output voltage accuracy from -40 c to +125 c ? highly efficient - 97 % peak efficiency - 1 a supply current at shutdown - 50 a operating current, not switching ? highly configurable - four programmable switchin g frequencies available: 300 khz, 500 khz, 750 khz, and 1 mhz - adjustable soft start and adjustable current limit - three modes of operation: forced continuous conduction, power save (sic431b, sic431d), or ultrasonic (sic431a, sic431c) ? robust and reliable - cycle-by-cycle current limit - output overvoltage protection - output undervoltage / short circuit protection with auto retry - power good flag and over temperature protection ? design tools - supported by vishay po wercad online design simulation ( www.vishay.com/power-ics/powercad-list/ ) - design support kit ( www.vishay.com/ppg?74589 ) ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 typical application circuit and package options fig. 1 - typical application circuit for sic431 fig. 2 - efficiency vs. output current (v in = 12 v, f sw = 500 khz, full load) v in p g ood en v dd s w p g nd a g nd c out v out v fb r up r down boot c boot v out pha s e v drv mode1 mode2 g l s ic431 input 3.0 v dc to 24 v dc c in 76 79 82 85 88 91 94 97 100 0 2 4 6 8 101214161820 efficiency (%) output current, i out (a) complete converter efficiency p in = v in x i in p out = v out x i out , mea s ured at output capacitor v out = 1.2 v, l = 0.36 h v out = 5 v, l = 1 h v out = 3.3 v, l = 1 h
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 2 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configuration fig. 3 - sic431 pin configuration pin description pin number symbol description 1, 2, 22, 26 v in input voltage 3, 4, 13, 27 p gnd power signal return ground 5 to 9 sw switching node signal; output inductor connection point 10, 11, 28 gl low side powe r mosfet gate signal 12 v drv supply voltage for internal gate driver. co nnect a 2.2 f decoup ling capacitor to p gnd 14 p good power good signal output; open drain 15 v dd supply voltage for internal logic. connect a 1 f decoupling capacitor to a gnd 16, 25 a gnd analog signal return ground 17 fb output voltage fee dback pin; connect to v out through a resistor divider network. 18 v out output voltage sense pin 19 en enable pin 20 mode2 soft start and current limit selection; connect a resistor to v dd or a gnd per table 2 21 mode1 operating mode and switching frequency selection; connect a resistor to v dd or a gnd per table 1 23 boot bootstrap pin; connect a ca pacitor to phase pin for hs po wer mosfet gate voltage supply 24 phase switching node signal for bootstrap return path ordering information part number part marking maximum current v dd , v drv light load mode operating junction temperature package SIC431AED-T1-GE3 sic431a 24 a internal ultrasonic -40 c to +125 c powerpak ? mlp44-24l sic431bed-t1-ge3 sic431b power saving sic431ced-t1-ge3 sic431c external ultrasonic sic431ded-t1-ge3 sic431d power saving 11 g l 12 v drv 13 p g nd 14 p g ood 15 v dd 16 a g nd 17 fb g l 10 s w 9 s w 8 s w 7 s w 6 s w 5 p g nd 4 p g nd 3 v in 2 v in 1 24 pha s e 23 boot 22 v in 21 mode1 20 mode2 19 en 18 v out 4 p g nd 3 p g nd 2 v in 1 v in 24 pha s e 23 boot 22 v in 21 mode1 20 mode2 19 en 18 v out g l 11 v drv 12 p g nd 13 p g ood 14 v dd 15 a g nd 16 fb 17 g l 10 s w 9 s w 8 s w 7 s w 6 s w 5 25 a g nd 26 v in 27 p g nd 28 g l pin 1 indicator
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 3 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 ? stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating/conditions for extended peri ods may affect de vice reliability. absolute maximum ratings (t a = 25 c, unless otherwise noted) electrical parameter conditions limits unit v in reference to p gnd -0.3 to +25 v v out reference to p gnd -0.3 to +22 v dd / v drv reference to p gnd -0.3 to +6 sw / phase reference to p gnd -0.3 to +25 sw / phase (ac) 100 ns; reference to p gnd -8 to +30 boot reference to p gnd -0.3 to +31 boot to sw -0.3 to +6 a gnd to p gnd -0.3 to +0.3 en reference to a gnd -0.3 to +25 all other pins re ference to a gnd -0.3 to +6 temperature junction temperature t j -40 to +150 c storage temperature t stg -65 to +150 power dissipation junction-to-ambient thermal impedance (r ? ja )16 c/w junction-to-case th ermal impedance (r ? jc )2 maximum power dissipation ambient temperature = 25 c 7.75 w esd protection electrostatic disc harge protection human body model 4000 v charged device model 1000 recommended operating conditions (all voltages referenced to a gnd , p gnd = 0 v) parameter min. typ. max. unit input voltage (v in ) (sic431a, sic431b) 4.5 - 24 v input voltage (v in ) (sic431c, sic431d) 3 - 24 logic supply voltage, gate driver supply voltage (v dd , v drv ) (sic431c, sic431d) 4.555.5 enable (en) 0 - 24 output voltage (v out )0.6- 0.9 x v in and < 20 v temperature recommended ambient temperature -40 to +105 c operating junction te mperature -40 to +125
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 4 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note (1) guaranteed by design electrical specifications (v in = 12 v, v en = 5 v, t j = -40 c to +125 c, unless otherwise stated) parameter symbol test condi tions min. typ. max. unit power supplies v dd supply v dd v in = 6 v to 24 v (sic431a, sic431b) 4.75 5 5.25 v v dd uvlo threshold, rising v dd_uvlo 33.33.6 v dd uvlo hysteresis v dd_uvlo_hyst -300- mv maximum v dd current i dd v in = 6 v to 24 v 3 - - ma v drv supply v drv v in = 6 v to 24 v (sic431a, sic431b) 4.75 5 5.25 v maximum v drv current i drv v in = 6 v to 24 v 50 - - ma input current i in non-switching, v fb > 0.6 v - 50 120 a shutdown current i in_shdn v en = 0 v - 0.5 3 controller and timing feedback voltage v fb t j = 25 c 597 600 603 m/v t j = -40 c to +125 c (1) 594 600 606 v fb input bias current i fb -2-na minimum on-time t on_min. -5065ns t on accuracy t on_accuracy -10 - 10 % on-time range t on_range 65 - 2250 ns minimum frequency, skip mode f sw_min. ultrasonic version (sic431a, sic431c) 20 - 30 khz power save ve rsion (sic431b, sic431d) 0 - - minimum off-time t off_min. 205 250 305 ns power mosfets high side on resistance r on_hs v drv = 5 v, t a = 25 c -6- m ? low side on resistance r on_ls -2- fault protections over current protecti on (inductor valley current) i ocp t j = -10 c to +125 c -20 - 20 % output ovp threshold v ovp v fb with respect to 0.6 v reference -20- output uvp threshold v uvp --80- over temperature protection t otp_rising rising temperature - 150 - c t otp_hyst hysteresis - 25 - power good power good output threshold v fb_rising_vth_ov v fb rising above 0. 6 v reference - 20 - % v fb_falling_vth_uv v fb falling below 0. 6 v reference - -10 - power good hysteresis v fb_hyst -40-mv power good on resistance r on_pgood -7.515 ? power good delay time t dly_pgood 15 25 35 s en / mode / ultrasonic threshold en logic high level v en_h 1.6 - - v en logic low level v en_l --0.4 en pull down resistance r en -5-m ? switching frequency mode1 (switching frequency) r mode1 f sw = 300 khz - 51 55 k ? f sw = 500 khz 90 100 110 f sw = 750 khz 180 200 220 f sw = 1000 khz 450 499 - soft start soft start time t ss connect r mode2 between mode2 and a gnd 1.8 3 4.2 ms connect r mode2 between mode2 and v dd 3.6 6 8.4 over current protection mode2 (over current protection) r mode2 i ocp = 32 a 450 499 - k ? i ocp = 24.8 a 180 200 220 i ocp = 17.3 a 90 100 110 i ocp = 9.6 a - 51 55
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 5 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram fig. 4 - sic431 functi onal block diagram regulator enable uvlo over voltage under voltage ramp on time generator zero cro ss ing over current over temperature power good a g nd p g nd v out v drv v dd en mode1 mode2 fb ea v in boot ph s w p g ood g l s ync. rectifier s oft s tart reference control logic s w v out r c c c r r v drv
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 6 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operational description device overview sic431 is a high efficiency synchronous buck regulator capable of delivering up to 24 a continuous current. the device has user programmable switching frequency of 300 khz, 500 khz, 750 khz, and 1 mhz. the control scheme delivers fast transient respon se and minimizes the number of external components. thanks to the internal ramp information, no high esr output bulk or virtual esr network is required for the loop st ability. this device also incorporates a power saving feature that enables diode emulation mode and frequency fold back as the load decreases. sic431 has a full set of protection and monitoring features: ? over current protection in pulse-by-pulse mode ? output over voltage protection ? output under voltage protection with device latch ? over temperature protection with hysteresis ? dedicated enable pin for easy power sequencing ? power good open drain output this device is available in mlp44-24l package to deliver high power density an d minimize pcb area. power stage sic431 integrates a high performance power stage with a 2 m ? n-channel low side mosfet and a 6 m ? n-channel high side mosfet. the mosfets are optimized to achieve up to 97 % efficiency. the input voltage (v in ) can go up to 24 v and down to as low as 3 v for power conversion. for input voltages (v in ) below 4.5 v an external v dd and v drv supply is required (sic431c, sic431d). for input voltages (v in ) above 4.5 v only a single input supply is required (sic431a, sic431b). control mechanism sic431 employs an advanced voltage - mode cot control mechanism. during steady-s tate operation, feedback voltage (v fb ) is compared with internal reference (0.6 v typ.) and the amplified error signal (v comp ) is generated at the internal comp node. an internal ly generated ra mp signal and v comp feed into a comparator. once v ramp crosses v comp , an on-time pulse is generated for a fixed time. during the on-time pulse, the high side mosfet will be turned on. once the on-time pulse expires, the low side mosfet will be turned on after a dead time period. the low side mosfet will stay on for a minimum duration equal to the minimum off-time (t off_min. ) and remains on until v ramp crosses v comp . the cycle is then repeated. fig. 5 illustrates the basic block diagram for vm-cot architecture. in this architecture the following is achieved: ? the reference of a basic ripple control regulator is replaced with a high again error amplifier loop ? this establishes two parallel voltage regulating feedback paths, a fast and slow path ? fast path is the ripple in jection which ensures rapid correction of the tr ansient perturbation ? slow path is the error amplif ier loop which ensures the dc component of the output voltage follows the internal accurate reference voltage fig. 5 - vm-cot block diagram all components for ramp si gnal generation and error amplifier compensation requir ed for the control loop are internal to the ic, see fig. 5. in order for the device to cover a wide range of v out operation, the internal ramp signal components (r x , c x , c y ) are automatically selected depending on the v out voltage and switching frequency. this method allows the ramp amplitude to remain constant throughout the v out voltage range, achieving low jitter and fast transient response. th e error amplifier internal compensation consists of a resistor in series with a capacitor (r comp , c comp ). fig. 6 demonstrates the basic operational waveforms: fig. 6 - vm-cot operational principle light load condition to improve efficiency at ligh t-load condition, sic431 provides a set of innovative i mplementations to eliminate ls recirculating current and switch ing losses. the internal zero crossing detector monitors sw node voltage to determine when inductor current starts to flow negatively. in power saving mode, as soon as in ductor valley current crosses zero, the device deploys diod e emulation mode by turning off low side mosfet. if load further decreases, switching frequency is reduced proportiona l to load condition to save switching losses while keeping output ripple within tolerance. the switching frequency is set by the controller to maintain regulation. in the st andard power save mode, there is no minimum switching frequency (sic431b, sic431d). for sic431a, sic431c, the minimum switching frequency that the regulator will reduce to is < 20 khz as the part avoids switching frequencies in the audible range. this light load mode implementation is called ultrasonic mode. input load s ic431 ripple ba s ed controller pwm comp ramp c x r x c y l v out v out c out error amp c comp r comp ref fb s w v in r up r down a g nd fixed on-time v ramp v comp pwm
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 7 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 mode setting, over current protection, switching frequency, and soft start selection the sic431 has a low pin count, minimal external components, and offers the user flexibility to choose soft start times, current limit setti ngs, switching frequencies and to enable or disable the ligh t load mode. two mode pins, mode1 and mode2, are user programmable by connecting a resistor from modex to v dd or a gnd , allowing the user to choose various operating modes. this is best explained in the tables below. output monitoring and protection features output over current protection (ocp) sic431 has pulse-by-pulse over current limit control. the inductor current is monitored during low side mosfet conduction time through r ds(on) sensing. after a pre-defined blanking time, the inductor cu rrent is compared with an internal ocp threshold. if indu ctor current is higher than ocp threshold, high side mo sfet is kept off until the inductor current falls below ocp threshold. ocp is enabled immediately after v dd passes uvlo rising threshold. fig. 7 - over-current protection illustration table 1 - mode1 configuration settings operation connection f switch (khz) r mode1 (k ? ) skip to a gnd 300 51 500 100 750 200 1000 499 forced ccm to v dd 300 51 500 100 750 200 1000 499 table 2 - mode2 configuration settings soft-start time connection i limit (%) r mode2 (k ? ) 3 ms to a gnd 30 51 54 100 78 200 100 (32 a) 499 6 ms to v dd 30 51 54 100 78 200 100 (32 a) 499 i load ocp thre s hold i inductor g h
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 8 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 output undervoltage protection (uvp) uvp is implemented by monitoring the fb pin. if the voltage level at fb drops below 0.12 v for more than 25 s, a uvp event is recognized and both high side and low side mosfets are turned off. after a duration equivalent to 20 soft start periods, the ic atte mpts to re-start. if the fault condition still exists, the above cycle will be repeated. uvp is active after the completion of soft start sequence. output overvoltage protection (ovp) ovp is implemented by monitoring the fb pin. if the voltage level at fb rising above 0.72 v, a ovp event is recognized and both high side and low si de mosfets are turned off. normal operation is resumed once fb voltage drop below 0.68 v. ovp is active after v dd passes uvlo ri sing threshold. over-temperature protection (otp) otp is implemented by monitoring the junction temperature. if the junction temperature rises above 150 c, a otp event is recognized an d both high side and low mosfets are turned off. after the junction temperature falls below 115 c (35 c hysteresis ), the device restarts by initiating a soft start sequence. sequencing of input / output supplies sic431 has no sequencing requirements on its supplies or enables (v in , v dd , v drv , en). enable the sic431 has an enable pin to turn the part on and off. driving the pin high enables th e device, while driving the pin low disables the device. the en pin is internally pulled to a gnd by a 5 m ? resistor to prevent unwanted turn on due to a floating gpio. pre-bias start-up in case of pre-bias startup, ou tput is monitored through fb pin. if the sensed voltage on fb is higher than the internal reference ramp va lue, control logic prevents high side and low side mosfets from switching to avoid negative output voltage spike and excessive current sinking through low side mosfet. fig. 8 - pre-bias start-up power good sic431s power good is an open-drain output. pull p good pin high through a > 10k resistor to use this signal. power good window is shown in the below diagram. if voltage on fb pin is out of this window, p good signal is de-asserted by pulling down to a gnd . to prevent false triggering during transient events, p good has a 25 s blanking time. fig. 9 - p good window diagram ? ? ? ? v out , 2 v/div v s w , 20 v/div v en , 2 v/div v ref (0.6 v) v fb v fb_ri s ing_vth_ov (typ. = 0.72 v) vfb_falling_vth_ov (typ. = 0.68 v) vfb_falling_vth_uv (typ. = 0.54 v) vfb_ri s ing_vth_u v (typ. = 0.58 v) p g pull-high pull-low
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 9 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics ? (v in = 12 v, v out = 1.2 v, f sw = 500 khz, c out = 47 f x 13, c in = 10 f x 6, unless otherwise noted) fig. 10 - efficiency vs. output current (v in = 12 v, f sw = 500 khz, full load) fig. 11 - efficiency vs. output current (v in = 12 v, f sw = 1000 khz, full load) fig. 12 - voltage reference vs. junction temperature fig. 13 - efficiency vs. output current (v in = 12 v, f sw = 500 khz, light load) fig. 14 - efficiency vs. output current (v in = 12 v, f sw = 1000 khz, light load) fig. 15 - en current vs. junction temperature 76 79 82 85 88 91 94 97 100 0 2 4 6 8 101214161820 efficiency (%) output current, i out (a) complete converter efficiency p in = v in x i in p out = v out x i out , mea s ured at output capacitor v out = 5 v, l = 1 h v out = 3.3 v, l = 1 h v out = 1.2 v, l = 0.36 h 76 79 82 85 88 91 94 97 0 2 4 6 8 101214161820 efficiency (%) output current, i out (a) 100 complete converter efficiency p in = v in x i in p out = v out x i out , mea s ured at output capacitor v out = 1.2 v, l = 0.19 h v out = 5 v, l = 0.47 h v out = 3.3 v, l = 0.36 h 592 594 596 598 600 602 604 606 608 -60 -40 -20 0 20 40 60 80 100 120 140 voltage reference, v fb (mv) temperature (c) 36 44 52 60 68 76 84 92 100 0.001 0.01 0.1 1 complete converter efficiency p in = v in x i in p out = v out x i out , mea s ured at output capacitor v out = 5 v, l = 1 h v out = 3.3 v, l = 1 h v out = 1.2 v, l = 0.36 h efficiency (%) output current, i out (a) 36 44 52 60 68 76 84 92 100 0.001 0.01 0.1 1 efficiency (%) output current, i out (a) complete converter efficiency p in = v in x i in p out = v out x i out , mea s ured at output capacitor v out = 1.2 v, l = 0.19 h v out = 3.3 v, l = 0.36 h v out = 5 v, l = 0.47 h 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -60 -40 -20 0 20 40 60 80 100 120 140 en current, i en (a) temperature (c) v en = 5.0 v
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 10 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics ? (v in = 12 v, v out = 1.2 v, f sw = 500 khz, c out = 47 f x 13, c in = 10 f x 6, unless otherwise noted) fig. 16 - en logic threshold vs. junction temperature fig. 17 - input current vs. input voltage fig. 18 - input current vs. junction temperature fig. 19 - shutdown current vs. input voltage fig. 20 - shutdown current vs. junction temperature fig. 21 - line regula tion vs. input voltage 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 en logic thre s hold, v en (v) temperature (c) v ih_en v il_en 20 30 40 50 60 70 80 90 100 0 3 6 9 12 15 18 21 24 27 30 input current, i vin (a) input voltage, v in (v) 20 30 40 50 60 70 80 90 100 -60 -40 -20 0 20 40 60 80 100 120 140 input current, i vin (a) temperature (c) 0.0 0.3 0.5 0.8 1.0 1.3 1.5 1.8 2.0 0 3 6 9 12 15 18 21 24 27 30 s hutdown current, i vin_ s hdn (a) input voltage, v in (v) 0.0 0.2 0.3 0.5 0.6 0.8 0.9 1.1 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 s hutdown current, i vin_ s hdn (a) temperature (c) -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 5 7 9 1113151719212325 line regulation (%) input voltage (v)
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 11 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics ? (v in = 12 v, v out = 1.2 v, f sw = 500 khz, c out = 47 f x 13, c in = 10 f x 6, unless otherwise noted) fig. 22 - load regulation vs. output current fig. 23 - on resistance vs. junction temperature -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 0.0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 load regulation (%) output current (a) 0 1.6 3.2 4.8 6.4 8.0 9.6 11.2 12.8 -60 -40 -20 0 20 40 60 80 100 120 140 on- s tate re s i s tance, r d s on (m ) temperature (c) high- s ide low- s ide
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 12 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics ? (v in = 12 v, v out = 1.2 v, f sw = 500 khz, c out = 47 f x 13, c in = 10 f x 6, unless otherwise noted) fig. 24 - startup with v in , t = 2 ms/div fig. 25 - shut down with v in , t = 100 ms/div fig. 26 - overcurrent protec tion behavior, t = 5 s/div fig. 27 - startup with en, t = 1 ms/div fig. 28 - shut down with en, t = 200 ms/div fig. 29 - output undervoltage protection behavior, t = 50 ms/div v dd , 5 v/div v p g ood , 5 v/div v in , 5 v/div v out , 500 mv/div v dd , 5 v/div v p g ood , 5 v/div v in , 5 v/div v out , 500 mv/div i out , 10 a/div v out , 500 mv/div v s w , 10 v/div v en , 5 v/div v dd , 5 v/div v p g ood , 5 v/div v out , 500 mv/div v en , 5 v/div v dd , 5 v/div v p g ood , 5 v/div v out , 500 mv/div v out , 500 mv/div v s w , 10 v/div
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 13 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics ? (v in = 12 v, v out = 1.2 v, f sw = 500 khz, c out = 47 f x 13, c in = 10 f x 6, unless otherwise noted) fig. 30 - load step, 12 a to 24 a, 1 a/s, t = 10 s/div fig. 31 - load step, 0.1 a to 12 a, 1 a/s, t = 10 s/div skip mode enabled fig. 32 - load step, 0.1 a to 12 a, 1 a/s, t = 10 s/div forced continuous conduction mode fig. 33 - load release, 24 a to 12 a, 1 a/s, t = 10 s/div fig. 34 - load release, 12 a to 0.1 a, 1 a/s, t = 50 s/div skip mode enabled fig. 35 - load release, 12 a to 0.1 a, 1 a/s, t = 20 s/div forced continuous conduction mode i out , 10 a/div s w, 10 v/div v out , 50 mv/div i out , 10 a/div s w, 10 v/div v out , 50 mv/div i out , 10 a/div s w, 10 v/div v out , 50 mv/div i out , 10 a/div s w, 10 v/div v out , 50 mv/div i out , 10 a/div s w, 10 v/div v out , 50 mv/div i out , 10 a/div s w, 10 v/div v out , 50 mv/div
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 14 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics ? (v in = 12 v, v out = 1.2 v, f sw = 500 khz, c out = 47 f x 13, c in = 10 f x 6, unless otherwise noted) fig. 36 - output rippl e, 0.1 a, t = 2 s/div forced continuous conduction mode fig. 37 - output ripple, 0.1 a, t = 20 s/div skip mode enabled fig. 38 - output ripple, 12 a, t = 1 s/div forced continuous conduction mode v out , 20 mv/div v s w , 10 v/div v out , 20 mv/div v s w , 10 v/div v out , 20 mv/div v s w , 10 v/div
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 15 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 example schematic for sic431 fig. 39 - schematic c vdd 1 f r _fb_l v out = 1.2 v at 24 a 9.53 k p g nd a g nd c out_d c out_c c out_b c out_a 100 f 100 f 100 f 100 f l o 300 nh 0.7 m c vdrv 4.7 f v in = 4.5 v to 24 v c in_d 100 nf c in 22 f x2 r boot 1r c boot 0.1 f r p g ood 10 k en p g ood * * analog ground (a g nd ), and power ground (p g nd ) are tied internally 100 k r mode2 499 k r mode1 10 k r _fb_h v dd a g nd v fb v out v in 1 v in-pad v in 2 v in 3 a g nd-pad p g nd-pad p g nd 1 p g nd 2 p g nd en pha s e boot p g ood g l 2 v drv s w 1 s w 2 s w 3 sic431 s w 4 s w 5 g l 1 mode1 mode2
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 16 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 external component selection for the sic43x this section explains external component selection for the sic43x family of regu lators. component reference designators in any equation re fer to the schematic shown in fig. 36. ? see powercad online design center to simplify external component calculations. output voltage adjustment if a different output voltage is needed, simply change the value of v out and solve for r _fb_h based on the following formula: where v fb is 0.6 v for the sic43x. r _fb_l should be a maximum of 10 k ? to prevent v out from drifting at no load. inductor selection in order to determine the indu ctance, the ripple current must first be defined. low inductor values allow for the use of smaller package sizes but create higher ripple current which can reduce efficiency. higher in ductor values will reduce the ripple current and, for a give n dc resistance, are more efficient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and efficiency are all used in the selection process. the ripple current will also set the boundary for power save operation. the sic431 will typi cally enter power save mode when the load current decrease s to 1/2 of the ripple current. for example, if ripp le current is 4 a, power save operation will be active for loads less than 2 a. if ripple current is set at 40 % of maximum load curre nt, power save will typically start at a load which is 20 % of maximum current. the inductor value is typically selected to provide ripple current of 25 % to 50 % of the maximum load current. this provides an optimal trade-off between cost, efficiency, and transient performance. during the on-time, voltage across the inductor is (v in - v out ). the equation for determining inductance is shown below. where, k is the maximum percentage of ripple current, d is the duty cycle, i out_max. is the maximum load current and f sw is the switching frequency. capacitor selection the output capacitors are chos en based upon required esr and capacitance. the maxi mum esr requirement is controlled by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. a change in the output ripple voltage will lead to a change in dc voltage at the output. for instance, the design goal for output voltage ripple is 3 % (45 mv for v out = 1.5 v) with ripple current of 4.43 a. the maximum esr value allowed is shown by the following equation. ? ? ? ? ? ? ? ? ? the output capacitance is usually chosen to meet transient requirements. a worst-case load release (from maximum load to no load) at the moment of peak inductor current, determines the required capacitance. if the load release is instantaneous (maximum load to no load in less than 1 s) the output capacitor must absorb all the inductors stored energy. the output capacitor can be calculated according to the following equation. ? ? ? ? where i out is the output current, i ripple_max. is the maximum ripple current, v pk is the peak v out during load release, v out is the output voltage. the duration of the load release is determined by v out and the inductor. during load release, the voltage across the inductor is approximately -v out , causing a down-slope or falling di/dt in the inductor. if the di/dt of the load is not much larger than di/dt of the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor; therefore a smaller capacitance can be used. under this circumstance, the following equation can be used to calculate the needed capacitance for a given rate of load release (di load /dt). ? ? ? ? ? ? ? ? r _fb_h r _fb_l v out - v fb ?? v fb ---------------------------------------------------- - = l o v in - v out ?? x d k x i out_max. x f sw ----------------------------------------------------- - = esr max. v ripple i ripple --------------------- 45 mv 4.43 a ----------------- == esr max. 10.2 m ? = c out_min. l o i out + 0.5 x i ripple max. ?? 2 v pk 2 - v out 2 ------------------------------------------------------------------------------ = c out l x i pk 2 v out --------------------- - i pk x i release ?? x dt di load ------------------ - 2v pk - v out ?? --------------------------------------------------------------------------------------------------- - = i pk i release + 1 2 -- - x i ripple max. ?? ?? =
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 17 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 where i pk is the peak inductor current, i ripple_max. is the maximum peak to peak inductor current, i release is the maximum load release current, v pk is the peak v out during load release, di load /dt is the rate of load release. if the load step does not meet the requirement, increasing the crossover frequency can help by adding feed forward capacitor (c ff ) in parallel to the uppe r feedback resistor to generate another zero and po le. placing the geometrical mean of this pole and zero around the crossover frequency will result in faster transient response. f z and f p are the generated zero and pole , see equations below. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? where r fb1 is the upper fee dback resistor, r fb2 is the lower feedback resistor c ff is the feed forward capacitor, f z is the zero from feed forward capacitor, f p is the pole frequency generated from the fe ed forward capacitor. a calculator is available to assist user to obtain the value of the feed forward capacitance value. from the calculator, obtain the crossover frequency (f c ). use the equation below for the calculation of the feed forward capacitance value. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? as the internal rc compensation of the sic431 works with a wide range of output lc filters, the sic431 offers stable operation for a wide range of output capacitance, making the product versatile and usable in a wide range of applications. input capacitance in order to determine the mi nimum capacitance the input voltage ripple needs to be specified; v cinpkpk ? 500 mv is a suitable starting point. this magnitude is determined by the final application specification. the input current needs to be determined for the lowest operating input voltage, the minimum input capacita nce can then be found, if high esr capacitors are used, it is good practice to also add low esr ceramic capacitance. a 4.7 f ceramic input capacitance is a suitable starting point. ? care must be taken to account for voltage derating of the capacitance when choosing an all ceramic input capacitance. f z 1 2 ? x r fb1 x c ff -------------------------------------------- - = f p 1 2 ? x r fb1 // r fb2 ?? x c ff ----------------------------------------------------------------------- = f c f z x f p ?? = c ff 1 2 ? x f c x r fb1 x r fb1 // r fb2 ?? ?? ?? ---------------------------------------------------------------------------------------------------- - = i cin rms ?? = i o x d x 1 d ? ?? 1 12 ------ v out l? sw i out ? ? ------------------------------------- ?? ?? 2 ? 1d ? ?? 2 ? d ? + c in_min. i out x d - 1 - d ?? v cinpkpk x f sw ----------------------------------------- =
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 18 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout recommendations step 1: v in /gnd planes and decoupling 1. layout v in and p gnd planes as shown above 2. ceramic capacitors shou ld be placed between v in and p gnd , and very close to the de vice for best decoupling effect 3. various ceramic capacitor values and package sizes should be used to cover enti re decoupling spectrum e.g. 1210 and 0603 4. smaller capacitance values, closer to v in pin(s), provide better high frequency response step 2: sw plane 1. connect output inductor to device with large plane to lower resistance 2. if a snubber network is required, place the components on the bottom layer as shown above step 3: v dd /v drv input filter 1. c vdd cap should be placed between v dd and a gnd to achieve best noise filtering 2. c vdrv cap should be placed close to v drv and p gnd pins to reduce effects of trace impedance and provide maximum instantaneous drive r current for low side mosfet during switching cycle step 4: boot resistor and capacitor placement 1. c boot and r boot need to be placed very close to the device, between phase and boot pins 2. in order to reduce para sitic inductance, it is recommended to use 0402 chip size for the resistor and the capacitor s w v in plane p g nd plane p g nd plane s w s nubber a g nd c vdd c vdrv p g nd cboot rboot
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 19 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 step 5: signal routing 1. separate the small analog sign al from high current path. as shown above, the high paths with high dv/dt, di/dt are placed on the left side of the ic, while the small control signals are placed on the right side of the ic. all the components for small analog signal should be placed closer to ic with minimum trace length 2. ic analog ground (a gnd ), pin 16, should have a single connection to p gnd . the a gnd ground plane connected to pin16 helps to keep a gnd quiet and improves noise immunity 3. the output signal can be routed through inner layers. make sure this signal is far away from sw node and shielded by an inner ground layer ? step 6: thermal management 1. thermal relief vias can be added to the v in and p gnd pads to utilize inner layers for high current and thermal dissipation 2. to achieve better thermal perf ormance, additional vias can be placed on v in and p gnd planes. it is also necessary to duplicate the v in and ground plane at bottom layer to maximize the power dissipation capability of the pcb 3. sw pad is a noise source an d it is not recommended to place vias on this pad 4. 8 mil vias on pads and 10 mil vias on planes are ideal via sizes. the vias on pad may drain solder during assembly and cause assembly issues. please consult with the assembly house for guideline ? step 7: ground connection 1. in order to minimize the ground voltage drop due to high current, it is recommended to place vias on the p gnd planes. make use of the inner ground layers to lower the impedance ? step 7: ground layer 1. it is recommended to make the whole inner 1 layer (next to top layer) ground plane 2. this ground plane provide s shielding between noise source on top layer and sign al trace within inner layer 3. the ground plane can be broken into two section, p gnd and a gnd p g nd a g nd plane v o u t s i g n a l v in plane p g nd plane s w vias vias p g nd plane a g nd plane
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 20 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package outline drawing powerpak ? mlp44-24l notes (1) use millimeters as the primary measurement (2) dimensioning and to lerances conform to asme y14.5m. - 1994 (3) n is the number of terminals (4) dimension b applies to plated terminal and is measured betw een 0.20 mm and 0.25 mm from terminal tip (5) the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package b ody (6) exact shape and size of this feature is optional (7) package warpage max. 0.08 mm (8) applied only for terminals dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.008 0.010 0.012 b1 0.15 0.20 0.25 0.006 0.008 0.010 d 3.90 4.00 4.10 0.155 0.157 0.159 e 0.45 bsc 0.018 bsc e1 0.70 bsc 0.028 bsc e2 0.90 bsc 0.035 bsc e 3.90 4.00 4.10 0.154 0.157 0.161 l 0.35 0.40 0.45 0.014 0.016 0.018 n (3) 24 24 d2-1 1.00 1.05 1.10 0.039 0.041 0.043 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.68 2.73 2.78 0.106 0.108 0.110 d2-4 2.02 2.07 2.12 0.079 0.081 0.083 d2-5 0.47 0.52 0.57 0.018 0.020 0.022 e2-1 0.95 1.00 1.05 0.037 0.039 0.041 e2-2 1.10 1.15 1.20 0.043 0.045 0.047 e2-3 0.33 0.38 0.43 0.013 0.015 0.017 e2-4 0.95 1.00 1.05 0.037 0.039 0.041 e2-5 0.27 0.32 0.37 0.011 0.013 0.015 k 0.40 ref. 0.016 ref. k1 0.57 ref. 0.022 ref. k2 0.35 ref. 0.014 ref. k3 0.35 ref. 0.014 ref. k4 0.35 ref. 0.014 ref. k5 0.525 ref. 0.021 ref. k6 0.725 ref. 0.029 ref. k7 0.575 ref. 0.023 ref. k8 0.975 ref. 0.038 ref. top view s ide view bottom view mlp44-24l (4 mm x 4 mm) b e c 0.08 a a1 a2 a c 0.10 a 2 x d pin 1 dot by marking (5) (6) 18 19 20 21 22 23 24 9 10 8 7 65 (4) c 0.10 ab m c 0.10 a 2 x k5 k5 e x 3 = 1.35 e1 e x 2 = 0.9 k4 l1 d2-2 d2-1 d2-3 d2-4 k1 l1 k3 d2-5 e x 2 = 0.9 k5 k8 ee e1 k2 e2-5 17 16 15 14 13 12 1 2 3 4 11 k7 b e2-3 e2-4 k6 k4 k4 l lk4 e2-1 e2-2 k4 k4 k e2 e e b1 e x 6 = 2.7
sic431 www.vishay.com vishay siliconix s18-0176-rev. c, 12-feb-18 21 document number: 74589 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package / ta pe drawings, part marking, and reliability data, see www.vishay.com/ppg?74589 . product summary part number sic431a sic431b sic431c sic431d description 24 a, 4.5 v to 24 v input, 300 khz, 500 khz, 750 khz, 1 mhz, synchronous buck regulator with ultrasonic mode and internal 5 v bias 24 a, 4.5 v to 24 v input, 300 khz, 500 khz, 750 khz, 1 mhz, synchronous buck regulator with power save mode and internal 5 v bias 24 a, 3 v to 24 v input, 300 khz, 500 khz, 750 khz, 1 mhz, synchronous buck regulator with ultrasonic mode (external 5 v bias) 24 a, 3 v to 24 v input, 300 khz, 500 khz, 750 khz, 1 mhz, synchronous buck regulator with power save mode (external 5 v bias) input voltage min. (v) 4.5 4.5 3.0 3.0 input voltage max. (v) 24 24 24 24 output voltage min. (v) 0.6 0.6 0.6 0.6 output voltage max. (v) 0.90 x v in 0.90 x v in 0.90 x v in 0.90 x v in continuous current (a) 24 24 24 24 switch frequency min. (khz) 300 300 300 300 switch frequency max. (khz) 1000 1000 1000 1000 pre-bias operation (yes / no) y y y y internal bias reg. (yes / no) y y n n compensation internal internal internal internal enable (yes / no) y y y y p good (yes / no) yyyy over current protection y y y y protection ovp, ocp, uvp/scp, otp, uvlo ovp, ocp, uvp/scp, otp, uvlo ovp, ocp, uvp/scp, otp, uvlo ovp, ocp, uvp/scp, otp, uvlo light load mode selectable ultrasonic selectable powersave selectable ultrasonic selectable powersave peak efficiency (%) 97 97 97 97 package type powerpak mlp 44-24l powerpak mlp 44-24l powerpak mlp 44-24l powerpak mlp 44-24l package size (w, l, h) (mm) 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75 status code 1111 product type microbuck (step down regulator) microbuck (step down regulator) microbuck (step down regulator) microbuck (step down regulator) applications computers, consumer, industrial, healthcare, networking computers, consumer, industrial, healthcare, networking computers, consumer, industrial, healthcare, networking computers, consumer, industrial, healthcare, networking
package information www.vishay.com vishay siliconix revision: 19-dec-16 1 document number: 74345 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 powerpak ? mlp44-24l case outline notes (1) use millimeters as the primary measurement (2) dimensioning and to lerances conform to asme y14.5m. - 1994 (3) n is the number of terminals (4) dimension b applies to plated terminal and is measured betw een 0.20 mm and 0.25 mm from terminal tip (5) the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package b ody (6) exact shape and size of this feature is optional (7) package warpage max. 0.08 mm (8) applied only for terminals dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.110 d 3.90 4.00 4.10 0.155 0.157 0.159 e 0.45 bsc 0.018 bsc e1 0.70 bsc 0.028 bsc e2 0.90 bsc 0.035 bsc e 3.90 4.00 4.10 0.155 0.157 0.159 l 0.35 0.40 0.45 0.014 0.016 0.018 l1 0.25 0.30 0.35 0.010 0.012 0.014 l2 0.83 0.88 0.93 0.033 0.035 0.037 n (3) 24 24 d2-1 1.00 1.05 1.10 0.039 0.041 0.043 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.68 2.73 2.78 0.106 0.108 0.110 d2-4 2.05 2.10 2.15 0.081 0.083 0.085 e2-1 0.95 1.00 1.05 0.037 0.039 0.041 e2-2 1.10 1.15 1.20 0.043 0.045 0.047 e2-3 0.52 0.57 0.62 0.020 0.022 0.024 e2-4 0.95 1.00 1.05 0.037 0.039 0.041 k 0.40 ref. 0.016 ref. k1 0.57 ref. 0.022 ref. k2 0.45 ref. 0.018 ref. k3 0.50 ref. 0.020 ref. k4 0.35 ref. 0.014 ref. ecn: t16-0945-rev. a, 19-dec-16 ? dwg: 6055 top view s ide view bottom view mlp44-24l (4 mm x 4 mm) b e c c 0.08 a a1 a2 a c 0.10 a 2 x d pin 1 dot by marking (5) (6) 18 19 20 21 22 23 24 e x 3 = 1.35 e x 2 = 0.9 e1 1 2 3 4 e e2 e e2-1 k4 k4 l k4 l e2-2 e2-4 k4 k4 e2-3 9 10 ee e1 e x 2 = 0.9 8 7 65 17 16 15 14 13 12 11 e x 6 = 2.7 (4) c 0.10 ab m b l k1 k4 k l1 d2-2 d2-1 d2-3 d2-4 k3 l2 k2 l1
pad pattern www.vishay.com vishay siliconix revision: 15-aug-17 1 document number: 78231 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern powerpak ? mlp44-24l all dimensions are in millimeters 24 18 510 1 4 17 11 24 18 510 1 4 17 11 1.15 0.3 1.575 0.3 0.25 2.825 0.5 0.65 0.27 0.58 0.3 0.55 2.175 0.45 0.3 0.725 0.3 0.525 0.9 0.7 0.45 0.45 0.975 0.3 4 1.025 0.45 0.9 0.45 1.175 0.3 0.3 0.725 0.3 0.45 0.73 0.575 0.45 x 6 = 2.7 0.725 0.3 1.05 0.3 0.725 0.3 0.3 1.2 0.27 0.38 0.39 0.455 0.3 0.45 0.525 0.525 0.7 0.45 x 2 = 0.9 0.45 x 3 = 1.35 4
legal disclaimer notice www.vishay.com vishay revision: 08-feb-17 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners. ? 2017 vishay intertechnology, inc. all rights reserved

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